To keep up with Moore's Law, transistor channel length and gate-oxide thickness scaling is pursued from process node to process node in CMOS technology. Aggressive scaling of the gate oxide thickness for higher transistor current and speed has intensified reliability issues related to silicon dioxide (SiO2) that is used as gate oxide. Due to scaling, electric field within the gate oxide grows larger which may cause breakdown of the gate oxide. In deep sub-micron silicon process nodes, like 45 nm, 32 nm, and other advanced process nodes, the transistor gate-oxide and junction voltage limit have reduced and there are more voltage design rules to follow to prevent gate-oxide breakdown resulting from electrical overstress (EOS). This is because of thinner gate-oxide and shorter channel length for the transistors.
To support higher voltage applications, thick gate-oxide transistors may be used. If there are different high voltage sources (e.g., 1.8V, 3.3V, etc.) for the chip, then different types of thick-gate transistors may be used for various speed requirements. For example, for circuits desiring higher speed thinner gate-oxide transistors may be used compared to circuits desiring lower speed. Having many flavors of transistors with different gate-oxide thicknesses in a particular process node is costly due to extra mask cost, yield, and reliability challenges in fabrication. To reduce this cost, circuits are designed to enable the usage of transistors to support voltage higher than its limit.
Usually, sensitive components in electronic systems and circuits in chips are protected from EOS in a number of ways. For example, a circuit is used to generate an intermediate-level voltage (e.g., 1.8V) to provide protection to transistors when a higher power supply (e.g., 3.3V) ramps up before a lower power supply (e.g., 1.8V). Intermediate-level voltage may be used to prevent any transistor junction from exceeding the breakdown voltage limit when the higher power supply (e.g., 3.3V) is powered up first followed by powering up of the lower power supply (e.g., 1.8V). One common way to generate this intermediate-level voltage is to use a step-down voltage regulator.
However, voltage regulators consume high power and may not be suitable for low power applications. Also, voltage regulators consume idle power to step down a higher power supply (e.g., 3.3V) to lower power supply (e.g., 1.8V) when the lower power supply is ramped down while the higher power supply continues to be supplied to the chip. Furthermore, voltage regulators may need EOS protection to prevent its transistors from exposure of higher power supply (e.g., 3.3V).